The amd athlon micro architecture

The original Athlon architecture was built with an emphasis on performance more than any other functionality. This is what makes AMD be a desirable processor. It has a micro-architecture that can execute up to nine distinct and concurrent RISC instructions. AMD calls this “ OPs”. Here is where Athlon really shines. The microarchitecture can execute 9 simultaneous RISC instructions (what AMD calls ” OPs”). However, It has been noted that the Athlon architecture works best with applications that have a low data-level concurrency. The block diagram below shows a summary of these and more features of the AMD. AMD employs large L1 caches. The data caches, as well as the L1 instructions, are usually two-way, 64KB caches. These data caches provide another data port with a 64-byte sequence. Additionally, the AMD uses a 16-way 256KB unified cache in the L2 cache. The L2 is propped by a very fast EV6 bus architecture. Athlon can process up to three distinct types of floating point instructions (i. e. FSTORE, FMUL, and FADD) concurrently. These floating point units are usually fully pipelined which means that some instructions can be started even before the queued ones are completed. This is one of the reasons why Athlon will in many occasion outperform Intel. For instance, a 1. 33GHZ Athlon can perform better than a 1. 5GHZ Pentium IV. Comparing the Athlon processor to Intel’s processors will yield some significant variations. According to Intel’s documentation, Intel’s processor will have “ the same hit rate as an 8K to 16K byte conventional instruction cache” (Agner 126).